The NRD-505's signal flow can easily be followed by analyzing each of the plug-in boards in the receivers RF section in the order in which they are used.

The input signal at the antenna input connector is applied to the RF FILTERS UNIT (CFL-66), the first module in the RF section. A 20 dB RF attenuator may be switched in line before a 35 MHz low pass filter, after which one of 6 RF filters is selected according to the operating frequency. These filters include a 1.6 MHz low-pass filter, and band-pass filters for the 1.6-3 MHz, 3-5 MHz, 5-8 MHz, 8-16 MHz and 16-30 MHz bands.

After the RF filters, the signal moves on to the RF AMPLIFIER UNIT(CAF-69) where it encounters a 35 MHz low pass filter and PIN diode attenuator used for AGC. The signal is then amplified by a wideband push-pull amp (TR1 and TR2). At the first balanced FET mixer (TR5 and TR6) the RF signal is mixed with the 1st local signal of 70.455-100.455 MHz from the LOOP 1 UNIT (CGA-23) to derive the first intermediate frequency (i.f.) of 70.455 MHz. The first i.f. signal is filtered by FL1 (a crystal filter), amplified by TR7 and applied to the second mixer (TR8) along with the second local signal of 70 MHz from the VFO SELECT-LOC OSC UNIT (CHC-4) to derive the second i.f. of 455 kHz, which is then amplified by IF amplifier TR12 and, at the same time, applied to the noise blanker circuit.

The noise blanker circuit on the RF AMPLIFIER UNIT circuit board is comprised of TR13-TR20. The 455 kHz signal from the second mixer is amplified by TR13 and TR14, then detected by TR15. A DC voltage proportional to the level of this signal is amplified by TR16 and TR17 and is applied to the bases of TR13 and TR14 as an AGC signal. Pulse noise exceeding the average level of the signal is rectified by TR18, amplified by TR19 and applied to the gate circuit of TR20, which succeeds TR12, to eliminate or reduce the pulse noise.

The 455 kHz signal from TR20 proceeds to the IF AMP UNIT (CAE-56) where it is filtered by one of the three selectable bandpass filters. FL1 is a 6 kHz ceramic filter (NTK type CLF-D6S) used for normal AM reception. FL2 is a 2.2 kHz mechanical filter SSB filter (Kokusai type MF-455-10AZ121) that can also be selected for narrow AM and wide CW operation. FL3 is an optional 600 Hz mechanical filter for narrow CW reception (Kokusai type MF-455-03AZ121). Filter selection is done automatically when the mode is selected by the front panel switch. Independent filter selection is not possible (i.e., the wide AM filter can not be used in the CW mode).

The filtered signal is then amplified by TR1-TR4 and applied to the detector circuit, the output from which is fed into a switching circuit and amplified by TR14 to produce an AF signal (in the case of non-AM signals, a beat frequency signal is provided by the BFO circuit on the BFO - AF Amp unit; see below). The signal from TR14 is also detected by CD20 and amplified by TR6 to derive the IF AGC signal which automatically adjusts the gain of all preceding RF and IF amplifiers.

The detected audio is finally applied to the BFO - AF AMPLIFIER UNIT (CGD-26) where it passes through an active audio filter comprised of TR5 and TR6. This filter is automatically selected when the mode switch is set to either cw(n) or cw(w), using diodes CD11 and CD12 as a switching circuit. Otherwise the filter is bypassed and th audio is fed directly to the AF amplifier comprised of IC1 and IC2. This amp stage feeds audio to the speaker, headphone, line out and record outputs.

The BFO circuit (TR1-TR4) produces the following beat signals:

Frequency synthesis is accomplished by the remaining circuit boards. The REFERENCE SIGNAL & VFO COUNTER UNIT (CBD-49) generates a 10 MHz reference signal (via IC20) and through frequency dividers IC1-IC5 and IC24 produces 5 MHz, 500 kHz, 100 kHz, and 100 Hz signals. A basic gate signal generator circuit consisting of IC6, IC22 and IC23, produces the various gate pulses necessary for the VFO counter circuit, which is a VFO buffer amplifier (TR1 & TR2), VFO counter (IC7-IC12), ratching circuit (IC13-IC17), and overlap detecting circuit (IC18 & IC19). Frequency information from the VFO counter circuit is sent to the INDICATOR UNIT (CDE-74). IC1-IC6 is a decoder which converts the BCD (binary-coded decimal) code to light the 7-segment light-emitting diodes (CD1-CD6) which serve as the frequency display. Overlap information is applied to either CD7 or CD8.

The VFO SELECTION AND LOCAL OSCILLATOR UNIT (CHC-4) operates precisely as its name implies. The VFO selection circuit (TR1-TR3, CD1-CD5, and IC2) operates to select the outputs of the internal and external VFOs and memory unit and to feed the signals to the synthesizer. The LO circuit uses oscillator TR7 and buffer amp IC5 to produce a second local signal of 70 MHz. The same signal is fed to mixer TR4 and mixed with a 5 MHz reference signal to produce another local signal of 65 MHz, which is amplified by TR5 and TR6 and fed into Loop 2.

A 13 MHz oscillator circuit of IC1 operates when the DF switch is turned on, and a harmonic wave of 65 MHz from the fundamental of 13 MHz is amplified by TR5 and TR6, then fed into Loop 2. IC3 and IC4 converts the level of the USB and LSB mode information.

The LOOP 1 (CGA-23) and LOOP 2 UNIT (CGA-24) circuit boards make up the major part of the frequency synthesizer. In the Loop 2 circuit, the 65 MHz signal (fed from CHC-4) is mixed at TR2 with an output signal of 67.455-68.455 MHz from the Loop 2 VCO to produce an output signal of 2.455-3.455 MHz, which is then fed to a phase detector (IC4). A reference signal from the output of the VFO UNIT (CGA-505) is also applied to IC4 and the phase difference between both signals is detected. The output of IC4 is coupled with varactor diodes in the Loop 2 VCO through a low pass filter to control the VCO frequency. When the phase of the signal fed from TR2 agrees with that of the reference signal in IC4, Loop 2 becomes locked and the LED (CD4) turns off.

In the Loop 1 unit, both signals of 67.455-68.455 MHz from Loop 2 and 70.455-100.4549 MHz from the Loop 1 VCO are applied to a balanced mixer (CD1-CD4) to produce the output signal of 3-32 MHz, while the output signal of the Loop 1 VCO is amplified to produce the first local signal which, as previously stated, is mixed with the incoming RF signal to produce the first i.f. of 70.455 MHz. The 3-32 MHz output signal fed from the mixer is passed through a 35 MHz low pass filter, amplified by IC2 and TR4, and fed to a variable frequency divider (IC16, IC19 and IC20) on the Loop 2 unit.

The 500 kHz signal from the variable frequency divider and is applied along with another 500 kHz signal to the phase detector (IC4) of the Loop 1 circuit board to detect phase difference. The output of the phase detector is passed through a low pass filter and is used to control the Loop 1 VCO.

When Loop 1 is out of lock, an LED (CD6) is lit. The circuit composed of IC7 and TR5-TR7 in the Loop 1 unit switches the power supply for oscillator circuits within the Loop 1 VCO.

A decoder circuit (IC7-IC15) on the Loop 2 unit selects the appropriate RF input filter and Loop 1 VCO oscillator circuit according to operating frequency.

The NRD-505 uses a clever drift cancellation system to eliminate 70 MHz reference signal drift. For example, if the operating frequency is 7.100 MHz and the 70 MHz crystal oscillator drifts +10Hz, the Loop 1, Loop 2 and first and second mixers act to cancel the drift as follows: The LO mixer output will be 65 MHz+10 Hz; Loop 2 VCO output will be 67.555 MHz+10 Hz; Loop 1 VCO output will be 77.555 MHz+10 Hz; and finally the first mixer output will be 70.455 MHz+10 Hz. The second mixer output is the difference between the first mixer output and the 70 MHz reference signal: (70.455 MHz+10 Hz) - (70 MHz+10 Hz) = 455 kHz; thus the 10Hz drift is canceled.

The MEMORY UNIT (CDD-48) stores BCD-encoded frequency information for up to four frequencies. The data for the 1 MHz and 10 MHz digits are sent to both the digital frequency indicator and the variable frequency divider in Loop 2. The data for digits below 1 MHz are applied to the PLL to control the frequency division and to produce the same 2.455-3.4549 MHz signal as the VFO. IC1-IC3 memorize the information, while IC8 and IC9 control the 1 MHz and 10 MHz digit information.

The output of the VCO (TR1) is fed to a variable frequency divider circuit (IC10-IC14), which is controlled by the information stored in the memory ICs. The output signal of the frequency divider and the 100 Hz reference frequency are compared with each other by phase detector IC23. The output of IC23 is applied to the VCO to control its output frequency, which is amplified by TR2 and fed to Loop 2 to produce the preset frequency.

The power supply circuit (T1, CD1, CD2, IC1 and IC2) feeds +5, +13 and +15V to the receiver's circuits. IC1 and IC2 are three-terminal voltage regulators.